1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor used in a liquid crystal display device.
2. Description of the Related Art
In recent years, active research and engineering development have been underway for applying a thin film active device formed on a glass substrate to various fields such as a large area transmission liquid crystal display and an adhesion type image sensor. In particular, a low-temperature polycrystalline silicon thin film transistor (TFT) has attracted attention as a most desirable device for realizing an integrated thin film device incorporating peripheral drive circuits.
FIGS. 1A through 1D are cross-sectional views showing a method of fabricating such a thin film transistor as a self-aligned planar thin film transistor in the order of steps. In this method, as; shown in FIG. 1A, a polycrystalline silicon film 14 is formed on a glass substrate 6 through a silicon oxide film 12.
Next, as shown in FIG. 1B, a gate insulating film 24 of a silicon oxide film is formed on the polycrystalline silicon film 14 so as to cover the polycrystalline silicon film 14. After a film of a material for an gate electrode is formed on the gate insulating film 24, the gate electrode film is etched together with the gate insulating film 24 provided under the gate electrode film, thereby forming a gate electrode 26.
Thereafter, as shown in FIG. 1C, the polycrystalline silicon film 14 is doped with impurities 28 using the gate electrode 26 as a mask and a source-drain region 30 is formed in a self aligned manner.
Further, as shown in FIG. 1D, a gate insulating film 24 is formed again on a whole surface of the device, an interlayer insulating film 32 is formed on the gate insulating film 24 and an electrode 36 is formed on the interlayer insulating film 32. The electrode 36 is connected to the source-drain region 30 through a contact hole 34 formed in the interlayer insulating film 32 and the gate insulating film 24. By doing so, a thin film transistor is completed.
In the above-stated conventional manufacturing method, however, if the gate electrode material as well as the gate insulating film 24 is etched, it is quite difficult to selectively etch the gate insulating film 24 since it is an oxide film of the polycrystalline silicon film 14. As a result, production yield is sometimes disadvantageously decreased.
The improved conventional technique to overcome the disadvantage is shown in FIGS. 2A to 2D. In FIGS. 2A to 2D, same reference numerals denote the same elements as those in FIGS. 1A to 1D and no detailed description is given thereto. As shown in FIG. 2B, a gate insulating film 24 is formed on the entire surface and then a gate electrode 26 is formed into a predetermined pattern.
Next, as shown in FIG. 2C, using the gate electrode 26 as a mask, impurities 28 are implanted into a polycrystalline silicon film 14 through the gate insulating film 24. Thereafter, as shown in FIG. 2D, an interlayer insulating film 32 and then an electrode 36 are formed.
Since this method does not require etching the gate insulating film 24, the above disadvantage related to etching process can be avoided.
However, the thickness of the gate insulating film 24 is normally about 1000 .ANG.. To implant impurities 28 into a semiconductor layer through the oxide film having such a thickness and provided on the semiconductor layer, it is necessary to accelerate the impurities 28 at a voltage of 100 keV or higher, so that a quite expensive impurity doping system is needed and investment cost is increased accordingly As a result, production cost is disadvantageously increased. Besides, when the impurities 28 are implanted at such high voltage, electrostatic damage easily occurs to the gate insulating film 24, thus deteriorating yield.
Meanwhile, we note that the following are already published as methods of manufacturing a thin film transistor. First, in the method described in Japanese Unexamined Patent Publication No. 6-333948, a gate insulating film is formed to include a stepped portion in a position wider than a gate electrode to thereby have different film thickness. Ion implantation is performed using the gate electrode and gate insulating film as masks. Thus, an LDD structural TET including an LDD region and a source-drain region can be obtained.
Japanese Unexamined Patent Publication No. 8-279620 discloses a thin film transistor manufacturing method in which an active region consisting of a polycrystalline silicon thin film, a source-drain region consisting of a low resistance region, a high resistance region for connecting the active region and the source-drain region are formed on an insulating substrate. In this method, the high resistance region is formed by implanting ions of non-mass separation type while cooling the substrate. Thus, the high resistance region can be formed under doping conditions of high accelerating voltage and high dosage.
Further, Japanese Unexamined Patent Publication No. 9-289318 discloses that a high resistance part having lower crystallinity than that of a channel region is formed on at least part of a drain region and a source region.
The thin film transistor manufacturing methods described in the above-cit-ed references, however, do not overcome the above-stated disadvantage.